Power conversion control circuit, power conversion control lsi, differential detection circuit, and pulse width control signal generation circuit

ABSTRACT

The control accuracy equal with the case controlled according to a reference signal with a high clock frequency when the electric power is converted is obtained according to a reference signal with a low clock frequency. 
     The quantity of signal S 3  of the time that corresponds to the difference of E O  in the output voltage to reference voltage EREF by circuit  12  of the generation of quantity of signal of time is generated synchronizing with reference timing signal S 1 . 
     The phase generates the class of the phase-shift signal of n piece for which only [Cycle of S 0 /]/n is late one by one by phase-shift signal generation circuit  13,  counter circuit  14 , and digital addition circuit  15 , these numbers are counted respectively, and the count value of n piece is added. 
     The control signal S 5  that corresponds to TON between when adding value ADD is input with decision circuit  16  of on time of the switch element and control signal generation circuit  17  and it turns it on is generated.

TECHNICAL FIELD

(1) Electric power conversion control circuit and LSI for electric power conversion control that can obtain the control accuracy equal with the case controlled according to reference signal by using low clock frequency, when the electric power is converted. (2) Difference detecting circuit that can detect difference of two voltage signals as digital value of high resolution accuracy, (3) Signal generation circuit for the pulse width control that can generate pulse width signal of high resolution accuracy corresponding to time concerned set value according to time given by integer value.

BACK GROUND OF THE TECHNICAL ART

Digital LSI including the microprocessor is being used for the electric power conversion control circuit (in this detailed statement, it is said, “electric power conversion control circuit”) such as the DC/DC converter for the following reasons.

(1)The influence by the temperature change is a little. (2) Various parameters can be set to programmable.

PROBLEM TO BE SOLVED BY THE INVENTION

So far, a electric power conversion control circuit is known. This electric power conversion control circuit replaces the difference between output voltage E_(O) and the reference voltage E_(REF) of the controlled object (target value voltage) with the time amount and detect it, and decides the duty of the control signal (rectangular wave) based on the time amount. This electric power conversion control circuit can control high accuracy by detecting the time amount by using the clock generator of the frequency of about 50 MHz or more.

Therefore, the clock generator with a high price is necessary to be controlled by the frequency of 50 MHz or more.

The purpose of the present invention is to offer electric power conversion control circuit and LSI for the electric power conversion control that can obtain detection accuracy equal with control according to reference signal with high clock frequency by using standard clock signal with low frequency.

Other purpose of this invention is to offer difference detection circuit that can obtain detection accuracy equal with control according to reference signal with high clock frequency by using standard clock signal with low frequency.

Other purpose of this invention is to offer pulse width control signal generation circuit can obtain detection accuracy equal with control according to reference signal with high clock frequency by using standard clock signal with low frequency.

MEANS FOR SOLVING PROBLEM

The present invention characterizes below.

(1) The electric power conversion control circuit that generates control signals corresponding to on-time (on period) of each switch element, comprising,

the first reference timing generation circuit that the first reference signal,

the time amount signal generation circuit that inputs the reference voltage and output voltage of power conversion circuit and generates the time amount signal corresponding to difference between standard said reference, and said output voltage synchronizing with said the first timing signal,

the phase shift signal generation circuit that inputs the reference clock signal, and generates the group that consists of n phase shift signals that the phase delays one by one by [one cycle of the reference clock signal]/n,

the count circuit that inputs n phase shift signals, counts these pulse numbers respectively synchronizing with the first reference timing signal, and outputs n count-values digitally when amount of signal of time is active,

the digital addition circuit that inputs said n count-values, adds these values, and outputs this adding value as a value corresponding to said time amount signal,

the switch element on-time deciding circuit that inputs said adding value, decides said on-time, and outputs as the integer value,

the second timing generation circuit that generates the second reference timing signal,

the control signal generation circuit that inputs said n phase shift signals synchronizing with said the second reference timing signal, generates the control signal of accuracy n time the reference clock signal corresponding to said on-time.

(2) The electric power conversion control circuit of (1) wherein, said phase shift signal generation circuit consists of the delay (n-1) circuits, and each delay circuit delays the phase one by one by [one cycle of the reference clock signal]/n, and generates said phase shift signal. (3) The electric power conversion control circuit of (1) or (2), wherein, said count circuits have,

n AND-gates that input the said time amount signal input to the first terminal and said phase shift signal input to the second terminal, and output these logical product,

n counters that count the output pulse from said n AND gate respectively, and output each count value digitally.

(4) The electric power conversion control circuit of (1), (2) or (3), wherein, said control signal generation circuit has, the distribute circuit that distributes said on-time value N₂ n to integers N₂₁, N₂₂, N₂₃, . . . , N_(2N),

time signal generation circuit that inputs a reference voltage and the output voltage of the electric power conversion circuit, and generates time amount signal corresponding to difference of said output voltage to said reference voltage synchronizing with said the first reference timing signal, so that the following requirement is met

N ₂₁ +N ₂₂ +. . . +N _(2n) =N ₂

N ₂₁ ≧N ₂₂ ≧. . . ≧N _(2n)

n counters that output the pulses of number corresponding to value that is preset for the phase to delay [one cycle of the reference clock signal]/n one by one,

the pulse synthesis circuit that synthesizes the output pulses of said counters, and outputs the synthesized signal as the control signal.

(5) The electric power conversion control circuit of (1), (2), (3), or 4, wherein, said electric power conversion circuit is the DC/DC converter. (6). LSI for electric power conversion control that is packaged from the electric power conversion control circuit of (1), (2), (3), 4, or 5. (7) The difference detecting circuit, comprising,

the reference timing generation circuit that generates the reference signal,

the time amount signal generation circuit that inputs voltage signals, and generates said output voltage synchronizing with said reference timing signal,

the phase shift signal generation circuit that inputs the reference clock signal, and generates the group that consists of n phase shift signals that the phase delays one by one by [one cycle of the reference clock signal]/n,

the count circuit that inputs n phase shift signals, counts these pulse numbers respectively synchronizing with the reference timing signal, and outputs n count-values digitally when amount of signal of time is active,

the digital addition circuit that inputs said n count-values, adds these values, and outputs this adding value as a value corresponding to said time amount signal.

(8) The pulse width control signal generation circuit, comprising, the reference timing generation circuit that the reference signal, the time amount signal generation circuit that inputs voltage signals, and generates said output voltage synchronizing with said reference timing signal,

the control signal generation circuit that inputs a time set value as an integral value, inputs n phase shift signals based on said reference clock signal synchronizing with the above-mentioned standard timing signal, and inputs said n phase shift signals synchronizing with said the second reference timing signal, generates the control signal of accuracy n time the reference clock signal corresponding to said time set value.

BRIEF DESCRIPTION OF DRAWING

FIG. 1 is a block diagram that shows the electric power conversion control circuit in the embodiment of the present invention.

FIG. 2 is a diagram that shows the electric power conversion system mounted the electric power conversion control circuit of the present invention.

FIG. 3 is a diagram for explaining the difference detecting circuit in the embodiment of the present invention.

FIG. 4 is a diagram for explaining the pulse width control signal generation circuit in the embodiment of the present invention.

FIG. 5 is a diagram that shows the timing generation circuit, the time amount generation circuit, the phase shift circuit and the count circuit in the electric power conversion control circuit.

FIG. 6 is a diagram that shows the digital addition circuit, the switch element on-time deciding circuit and the control signal generation circuit in the electric power conversion control circuit.

FIG. 7 is a timing chart for explaining the operation of the electric power conversion control circuit shown in FIG. 3 and FIG. 4.

FIG. 8 is timing chart explaining the operation of the electric power conversion control circuit shown in FIG. 3 and FIG. 4.

FIG. 9 is another timing chart explaining the operation of the electric power conversion control circuit shown in FIG. 3 and FIG. 4.

FIGS. 10(A),(B),(C) are the diagrams that show another embodiment for improving the high accuracy and the speed-up.

FIG. 11 is a timing chart that shows the operation of the first integration circuit for the voltage detection and the second integration circuit for the voltage detection.

EFFECT OF THE INVENTION

By using the electric power conversion control circuit and LSI for the electric power conversion control of the present invention, when the electric power is converted the control, the accuracy equal with the control according to a reference signal with a high clock frequency can be obtained from the reference clock signal with low frequency.

By using the difference detecting circuit of the present invention, the detection accuracy equal with the control according to a reference signal with a high clock frequency can be obtained from the reference clock signal with low frequency.

By using the pulse width control signal generation circuit of the present invention, the control accuracy equal with the control according to a reference signal with a high clock frequency can be obtained from the reference clock signal with low frequency.

EXAMPLE

FIG. 1 is a diagram for explaining the embodiment of the present invention.

The electric power conversion control circuit 1 is packaged in LSI for the electric power conversion control, and generates control signal S₅ corresponding to on-time T_(ON). The control signal S5 generated by the electric power conversion control circuit 1 is sent to the drive circuit 120, and the drive circuit 120 sends the driving signal DRV to the electric power conversion circuit 100.

In this embodiment the electric power conversion circuit 100 is possible to apply to the electric power conversion circuit output as direct current. The circuit 100 can be apply to the DC/DC converter typically, though the circuit 100 can be apply to AC/DC converter too.

The electric power conversion control circuit 1 has the timing generation circuit 11, the time amount circuit signal generation circuit 12, the phase-shift signal generation circuit 13, the counter circuit 14, the digital addition circuit 15, the switch element on-time decision circuit 16, and the control signal generation circuit 17.

The timing generation circuit 11 generates the reference timing signal S₁. The cycle of on-off of the electric power conversion circuit 100 is decided depending on the reference timing signal S₁.

The time amount signal generation circuit 12 inputs the reference voltage E_(REF) and the voltage output E_(O) of the electric power conversion circuit 100, and generates the time amount signal S₃ corresponding to the difference of the output voltage E_(O) to reference voltage E_(REF) synchronizing with reference timing signal S₁. The CR Circuits of two sets (Refer to FIG. 3) described later can be typically used to convert the difference of the output voltage E_(O) to the reference voltage E_(REF) into the time amount signal S₃. Moreover, the time amount signal generation circuit 12 can have the distinction circuit that judges whether the output voltage E_(O) is large or small compared with the reference voltage E_(REF).

The phase-shift signal generation circuit 13 inputs the reference clock signal S₀. And, the phase-shift signal generation circuit 13 generates the set of n phase-shift signal S₄₁, S₄₂, . . . , S_(4n) that the phase delays only [one cycle T₀ of the reference clock signal S₀]/n one by one from the reference clock signal S₀.

The counter circuit 14 inputs n phase-shift signal S₄₁, S₄₂, . . . , S_(4n) when the time amount signal S₃ is active, counts the pulse numbers respectively synchronizing with the reference timing signal S₁, and outputs n count-values N₁₁, N₁₂, . . . , N_(1n) digitally.

The digital addition circuit 15 inputs n count-values N₁₁, N₁₂, . . . , N_(1n), adds these values, and outputs the adding value ADD digitally as a value that corresponds to the time amount signal S₃.

The switch element on-time decision circuit 16 inputs the adding value ADD, decides the on-time T_(ON) of the switch element (not shown in the figure) of the electric power conversion circuit 100, and outputs T_(ON) digitally as integral value N₂.

The control signal generation circuit 17 inputs n phase-shift signal S₄₁, S₄₂, . . . , S_(4n) synchronizing with reference timing signal S₁, generates the control signal S₅ n times accuracy of the reference clock signal S₀ corresponding to on-time T_(ON).

FIG. 2 shows the electric power conversion system 200 mounted the electric power conversion control circuit 1. The electric power conversion system 200 consists of the electric power conversion circuit (in FIG. 2, the electric power conversion circuit is the DC/DC converter 101 of step down type), the electric power conversion control circuit 1, and the drive circuit 120.

The DC/DC converter 101 consists of the transistor Tr for switching, the inductor L, the diode D, and the capacitor C. The transistor Tr and the inductor L are connected with the series between the input terminal a₁ and the output terminal b₁ (input terminal a₂ and output terminal b₂ are connected to the ground GND). The diode D is connected between the terminal on the inductor L side of the transistor Tr and the ground GND. The capacitor C is connected between the output terminal b₁ and b₂. In FIG. 2, the DC power E_(i) is connected with the input side of the DC/DC converter 101 (between the input terminal a₁ and a₂), and the load R is connected with the output side (between the output terminal b₁ and b₂).

The electric power conversion control circuit 1 inputs the output voltage E_(O) of the DC/DC converter 101, outputs the control signal S5 to drive circuit 120, and the drive circuit 120 sends driving signal to the transistor Tr of the DC/DC converter 101.

FIG. 3 shows a block diagram of the difference detecting circuit of the present invention.

In FIG. 3, the difference detecting circuit 2 consists of the timing generation circuit 21, the time amount signal generation circuit 22, the phase-shift signal generation circuit 23, the counter circuit 24, and the digital adding circuit 25.

The timing generation circuit 21 generates the reference timing signal S₁.

T the time amount signal generation circuit 22 inputs 2 voltage signal E_(A) and E_(B), and generates the time amount signal S₃ corresponding to the difference (E_(B)−E_(A)) synchronizing with reference timing signal S₁.

The phase-shift signal generation circuit 23 inputs the reference clock signal S₀, and generates the set of n phase-shift signal S₄₁, S₄₂, . . . , S_(4n) that the phase delays only [one cycle T₀ of the reference clock signal S₀]/n one by one from the reference clock signal S₀.

The counter circuit 24 inputs the time amount signal S₃ and n phase-shift signals S₄₁, S₄₂, . . . , S_(4n) when the time amount signal S₃ is active, counts these pulse numbers synchronizing with the reference timing signal respectively, and outputs n count-values N₁₁, N₁₂, . . . , N_(4n) digitally.

The digital adding circuit 25 inputs, adds n count-values N₁₁, N₁₂, . . . , N_(4n), and outputs this adding value digitally as a value corresponding to the time amount signal.

FIG. 4 shows a block diagram of the pulse width control signal generation circuit of the present invention.

In FIG. 4, the pulse width control signal generation circuit 3 consists of the timing generation circuit 31, the phase-shift signal generation circuit 32, and the control signal generation circuit 33.

The timing generation circuit 31 generates the reference timing signal S₁.

The phase-shift signal generation circuit 32 inputs the reference clock signal S₀, and generates n phase-shift signals S₄₁, S₄2, . . . , S_(4n) that each phase delays one by one by [one cycle T₀ of the reference clock signal S₀]/n from the reference clock signal S₀. Moreover, the phase-shift signal generation circuit 32 consists of (n-1) delay circuits. Each delay circuit delays the phase one by one by [one cycle T₀ of the reference clock signal S₀]/n, and generates the phase-shift signals S₄₁, S₄₂, . . . , S_(4n).

The control signal generation circuit 33 inputs a time set value as integral value N₂, inputs n phase-shift signals S₄₁, S₄₂, . . . , S_(4n) based on reference clock signal S₀ synchronizing with the reference timing signal S₁, and generates the pulse width control signal S_(p) (corresponding to the T_(ON) time) of accuracy n time the reference clock signal corresponding to the time setting value (integer N₂).

MODE FOR CARRYING OUT THE (CLAIMED) INVENTION

The composition and the operation of the electric power conversion control circuit 1 mentioned above are explained by the circuit diagrams of FIG. 5-6, and the timing charts of FIG. 7-9 in detail as follows.

FIG. 5 shows the timing generation circuit 11, the time amount signal generation circuit 12, the phase-shift signal generation circuit 13 and the counter circuit 14 included in the electric power conversion control circuit 1. Moreover, FIG. 6 shows the digital adding circuit 15, the switch element on-time decision circuit 16, and the control signal generation circuit 17.

The counter 111 generates the reference timing signal S₁ corresponding to the preset value (the digital value PS that is the setting value of the switching frequency). The on/off frequency of the control signal S₅ is decided by the frequency of the reference timing signal S₁ (100 kHz order). Above on/off frequency is generated by the control signal generation circuit 17.

The reference timing signal S₁ is generated from the reference clock signal S₀ described later. The reference timing signal S₁ is sent to the transistor switch Tr₁ of the voltage input circuit 121 and the transistor switch Tr₂ of the voltage input circuit 122. The voltage input circuit 121 inputs the output voltage E_(o), and the voltage input circuit 122 inputs the reference voltage E_(REF). The counter 111 generates The counter 111 composes timing generation circuit 11 of FIG. 1.

The voltage input circuit 121 consists of the input resistance r₁, the capacitor C₁, the transistor switch Tr₁, and the comparator C_(mp1). The output voltage E_(O) is given to one side terminal of the input resistance r₁. The capacitor C₁ is connected between the other terminal and the ground. The reference voltage input circuit 122 consists of the input resistance r₂, the capacitor C₂, the transistor switch Tr₂, and the comparator Cmp₂. The reference voltage E_(REF) is given to one side terminal of the input resistance r₂. The capacitor C₂ connects between the other terminal of the input resistance r₁ and the ground GND. The comparator Cmp₂ inputs the threshold value voltage V_(TB). The reference timing signal is given to the transistor switch Tr₁ and Tr₂. Moreover, the output terminal of comparator Cmp1 and the output terminal of the comparator Cmp2 are connected to EXOR gate 123.

When the reference timing signal S₁ turns off the transistor switch Tr₁ and Tr₂, as shown in FIG. 7, the voltage V₁₁ (the input signal of the comparator Cmp₁) of the capacitor C₁ rises and the voltage V₁₂ (the input signal of the comparator Cmp₂) of the capacitor C₂ rises. As shown in FIG. 7, the S₂₁ downs when the terminal voltage V11 reaches the threshold voltage V_(TH), and the S₂₂ rises when the terminal voltage V₁₂ reaches the threshold voltage V_(TH).

The input circuit 121 and the reference voltage input circuit 122 can be composed of the voltage controlled oscillator (VCO) that acts according to the timing of S₁. The input voltage is higher, so the voltage controlled oscillator (VCO) outputs the first pulse earlier. Therefore, the VCO that the oscillation cycle is large can be operated as well as the above integration circuit. Moreover, the output of EXOR gate 123( time amount signal S₃) outputs the time difference between the down edge of the signal S₂₁ and the down edge of S₂₂ as shown in FIG. 7.

The signal S₂₁ and S₂₂ are input to the digital filter 161 described later, and the digital filter 161 detects a time relation of the down edge of signal S₂₁ and the down edge of S₂₂. The voltage input circuit 121, the reference voltage input circuit 122, and the EXOR gate 123 compose the circuit 12 of the time amount generation signal in FIG. 1.

Three delay circuits 13(1), 13(2), 13(3) delay the phase one by one by [one cycle of the reference clock signal S₀]/4 to the reference clock signal S₀ (in FIG. 7, it is the phase-shift signal S₄₁), and generate the phase-shift signal S₄₂, S₄₃, . . . , S₄₄. The signal line of reference clock signal S₀ (the signal line of the phase-shift signal S₄₁) and three delay circuits 13(2), 13(3), 13(4) compose the phase-shift signal generation circuit 13 in FIG. 1.

The output signal of the EXOR gate 123 (the time amount signal S₃) is input to one side input terminal of the AND gate (And₁, And₂, And₃, and And₄), and the phase-shift signals (S₄₁, S₄₂, S₄₃, S₄₄) are input to the other input terminal of the AND gate (And₁, And₂, and And₃, And₄) respectively.

The AND gate (And₁, And₂, And₃, and And₄) outputs the logical product of these input signals by the pulse respectively.

The counter (parallel conversion type) 14(1), 14(2), 14(3), 14(4) counts the output pulses from the AND gate (And₁, And₂, And₃, and And₄) respectively and outputs the count values (N₁₁, N₁₂, N₁₃, N₁₄) as digital signal respectively.

In FIG. 8 indicates the case that the count value N₁₁ is “4”, N₁₂ is “4”, N₁₃ is “3” and N₁₄ is “3”. The counter (14(1), 14(2), 14(3), 14(4)) and the AND gate (And₁, And₂, And₃, and And₄) compose the counter circuit 14 of FIG. 1. The count value (N₁₁, N₁₂, N₁₃, N₁₄) is output to the adding circuit ADDER as shown in FIG. 6, and the adding circuit ADDER outputs the total value “N₁₁+N₁₂+N₁₃+N₁₄(4+4+3+3=14)” as the adding value ADD. This adding value ADD is a value (that is, the value corresponding to the difference of the output voltage E_(O) to the reference voltage E_(REF)) corresponding to time amount signal S₃ mentioned above. The adding circuit ADDER composes the digital adding circuit 15 shown in FIG. 1.

The digital filter 161 inputs the adding value ADD, decides the on-time T_(ON) of the switch elements of the DC/DC converter 101 (refer to FIG. 2) as a integer value, and outputs the on-time T_(ON) as integer values N₂.

Moreover ,digital filter 161 can preset the offset value, the gain, and the cutoff frequency, etc.

In addition, the digital filter 161 inputs the signal S₂₁ and S₂₂ as mentioned above, and judges the time relation of the down edge of S₂₁ and the down edge of the signal S₂₂ (that is, the output voltage E_(O) of the electric power conversion circuit 100 is whether larger or smaller than the reference voltage E_(REF)).

For instance, the output of digital filter 161 (integer value N₂) is a value corresponding to the control quantity like

[A/(1+Sτ)]×(E_(REF)−E_(O))

(A: constant, s: Laplace operator, τ: time constant)

The output of the digital filter 161 corresponds to the on-time of the next cycle of the reference timing signal S₁. The digital filter 161 composes the switch element on-time decision circuit 16 in FIG. 1.

The distribution circuit 171 distributes the on-time T_(on) input to four integers N₂₁, N₂₂, N₂₃,N₂₄.

The four integers N₂₁, N₂₂, N₂₃ satisfy the following expression,

N ₂₁ +N ₂₂ +N ₂₃ +N ₂₄ =N ₂

N ₂₁ ≧N ₂₂ ≧N ₂₃ ≧N ₂₄

In the present embodiment, when N₂ is 22 (N₂=22) it becomes N₂₁=6, N₂₂=6, N₂₃=5, and N₂₄=5 in as shown in FIG. 9.

Four counters 172(1), 172(2), 172(3), 172(4) are down counters, integer N₂₁, N₂₂, N₂₃, and N₂₄ are preset in each counter. When the pulses of the number preset are input, each counter outputs the pulses that the phase delays [one cycle of the reference clock signal S₀]/4 one by one.

The pulse synthesis circuit 173(flip-flop register FF) is set by the reference timing signal S₁, outputs the rising edge (up edge) of the control pulse S5. The pulse synthesis circuit 173 outputs the down edge of the control signal S₅ by the last pulse that counter s(172(1), 172(2), 172(3), 172(4)) output.

The distribution circuit 171, the counter (172(1), 172(2), 17(3), 172(4)), and the pulse synthesis circuit 173 compose the control signal generation circuit 17 in FIG. 1.

It explains the embodiment of the present invention more in detail as follows.

As shown in FIG. 10(A), the first integration circuit (for the voltage detection) 211, 212 of N(It is N=2 here) can be used. By delaying the operation timing of the first integration circuit 211 and 212 for the time of Tp/N by the delay x, the accuracy of the voltage detection rises, and the operation is speed-up. Moreover, the first integration circuit (for the voltage detection) 211, 2222 of N(N=2) and the second integration circuit (for the voltage detection) 221,222 of N(N=2) can be used as shown in FIG. 10(C). By shifting the operation timing of the integration circuit 211, 212, 221, 222 for the time of Tp/N by the delay x, the accuracy of the voltage detection rises, and the operation is speed-up.

In the said example, the voltage deviation will be detected once in one cycle of the on-off of the transistor switch (the digital numerical value N_(RM) to control the current control circuit 3 is detected once). However, the numerical value NRM digital may be detected two or more times in one cycle T_(e) of the first clock S_(e) as shown in FIG. 11.

In FIG. 11, the difference ΔNR of the coefficient value recorded will be detected two or more times (The measurement value is indicated four times here it with ΔNR1, ΔNR2, ΔNR3, and ΔNR4) in one cycle T_(e) of the first clock S_(e). 

1-8. (canceled)
 9. The pulse width control signal generation circuit that generates control signals corresponding to on-time (on period) of each switch element, comprising, the phase shift signal generation circuit that inputs the reference clock signal, and generates the group that consists of n phase shift signals that the phase delays one by one by [an one cycle of the reference clock signal]/n, the first reference timing generation circuit that the first reference signal, the control signal generation circuit that inputs said n phase shift signals synchronizing with said the second reference timing signal, generates the control signal of accuracy n time the reference clock signal corresponding to said on-time, wherein, the said control signal generation circuit has, the distribute circuit that distributes said on-time value N₂ n to integers N₂₁, N₂₂, N₂₃, . . . , N_(2N), so that the following requirement is met N ₂₁ +N ₂₂ +. . . +N _(2n) =N ₂ N ₂₁ ≧N ₂₂ ≧. . . ≧N _(2n) n counters that output the pulses of number corresponding to value that is preset for the phase to delay [one cycle of the reference clock signal]/n one by one, the pulse synthesis circuit that synthesizes the output pulses of said counters, and outputs the synthesized signal as the control signal.
 10. The pulse width control signal generation circuit of claim 9 wherein, said phase shift signal generation circuit consists of the delay (n-1) circuits, and each delay circuit delays the phase one by one by [one cycle of the reference clock signal]/n, and generates said phase shift signal.
 11. The electric power conversion control circuit using the said pulse width control signal generation circuit, of claim 9 wherein, the second timing generation circuit that generates the second reference timing signal, the time amount signal generation circuit that inputs the reference voltage and output voltage of power conversion circuit and generates the time amount signal corresponding to difference between standard said reference, and said output voltage synchronizing with said the second timing signal, the count circuit that inputs n phase shift signals, counts these pulse numbers respectively synchronizing with the first reference timing signal, and outputs n count-values digitally when amount of signal of time is active, the digital addition circuit that inputs said n count-values, adds these values, and outputs this adding value as a value corresponding to said time amount signal, the switch element on-time deciding circuit that inputs said adding value, decides said on-time, and outputs as the integer value.
 12. The electric power conversion control circuit of claim 11, wherein, said count circuits have, n AND-gates that input said time amount signal input to the first terminal and said phase shift signal input to the second terminal, and output these logical product, n counters that count the output pulse from said n AND gate respectively, and output each count value digitally.
 13. The electric power conversion control circuit of claim 11, wherein, said electric power conversion circuit is the DC/DC converter.
 14. LSI for electric power conversion control that is packaged from the electric power conversion control circuit of claim
 11. 